Charge-transfer display system

ABSTRACT

A matrix in which each row comprises a charge transfer register, a number of display elements equal to the number of register stages, and modulators responsive to information stored in each register for controlling the amount of excitation received by the display elements for that register.

United States Patent [191 Weimer [4 1 Feb. 11,1975

[54] CHARGE-TRANSFER DISPLAY SYSTEM 3,493,957 2/1970 Brooks 340/3363,564,135 2/1971 Weimer 315/169 TV [75] Inventor: Paul Kessler Wermer,Princeton, 3 643 106 2/1972 Berwin et a] l 307/22] D N I v I73]Assignee: RCA Corporation, New York. NY. Primary Examiner David L.Trafton [22] Filed: June 22, 1973 Attorney, Agent, or Firm-H.Christoffersen; S. Cohen [21] Appl. No.: 372,650

[52] us. Cl 340/324 R, 178/7.3 D, 307/221 D, [57] ABSTRACT 51 I t Cl315/169 A matrix in which each row comprises a charge trans- M 334 ferregister, a number of disp1ay elements equal to the 1 a g fz /ig i lv178/7 3 235/92 i number of register stages, and modulators responsive307/221 to information stored in each register for controlling theamount of excitation received by the disp1ay ele- [56] References Citedments for that register.

UNITED STATES PATENTS 11 Claims, 6 Drawing Figures 3,021,387 2/1962Rajchman 178/73 D i r W DISPLAY DISPLAY DISPLAY ELEMENT 36a ELEMENTELEMENT (Egg/ L SCAN F 00' W0 1 i WM U R 5| I P *1 g P i ELEMENTS 5noriiib iim L J F I L IL L 1 i 16m 49 M154 56 0., as 1 5+ {5L1 1 I N a Ng REGISTER i 40 300 5 52 =f- L ,/|0u I r I 3 t L L e 1 E A? *E E v2RETURN BIAS FORMODULATOR I l l l .L I. 1 2 JL =11 l i APHJ N l 1 POWER 542 i L I 1' I T I SUPPLY J- g BIAS FOR L J' i i HORCLOCK 5 BIAS FORVIDEO 7 a tl 1 INPUT GATE L 1 VIDEO SIGNAL SOURCE VERTICAL B CLOCKPTJENTEU 11975 v 3.866.209

SHEET 1 OF 4 DISPLAY ELEMENTS, ONE PER REGISTER STAGE pOwER REGISTERCONTROLLED MODULATOR ELEMENTS, SUPPLY ONE PER REGISTER STAGE L VIDEOSIGNAL CHARGE TRANSFER REGISTER W l0 S0uRGE sRlETvoLTAGE, T4

SouRGE .PTG RETURN BIAS SUPPLY Fia. 4

SHEET 2 [IF 4 PEER-[TED FEB I 1 I975 53a 3:? N CT 22225;

$22; a ,m I 4 222225 5222 m 1 Ema m 2 $22 n 5 W 55252 n 22%;: N n

J m a n s E n @22 Moss u 16% EMF IEE- wow @5251 1 I Q 1 E m N? i? E 1238: IIIIIIIIIIIIIIIIIIIII I -IL N9 2%. EIL Us 23225 52% FEE a 5%: an H:22 5% 5% CHARGE-TRANSFER DISPLAY SYSTEM There are many types of'displaysystems in which the signal information arrives in serial fashion and isto be displayed in parallel. Television is one example. This applicationdeals with a solid state displayof this general type and which isself-scanned.

The invention is illustrated in the drawings of which:

FIG. 1 is a block diagram of one embodiment of the present invention;

FIG. 2 is a block and schematic circuit diagram of an embodiment of theinvention;

FIG. 3 is a schematic diagram of a switch which may be used in thecircuit of FIG. 2;

FIG. 4 is a schematic diagram of a modified portion of the circuit ofFIG. 2;

FIG. 5 is a block and schematic circuit diagram of another form of theinvention; and

FIG. 6 is a drawing of waveforms for the operation of the circuit ofFIG. 2. i

The system shown in FIG. 1 includes a charge transfer register 10whichreceives input information from signal source 12. The register 10 may beone of the bucket brigade type or of the charge-coupled device (CCD)type. The shift voltage source 14 connected to the register supplies theshift voltages necessary to transfer the stored information. In theembodiment illustrated in FIG. 2, the shift voltage source is a bipolarhorizontal clock voltage source (the voltage swings both positive andnegative relative to ground). However, in other embodiments of theinvention, the shift voltage source may be a two, three or four or morephase power supply.

The stages of the charge transfer register (FIG. 1) connect to thecontrol elements of a plurality of modulator elements. These areillustrated by the single block 16. Each modulator element is connectedto a display element, the group of display elements being shownschematically by the single block 18. Power supply connects through therespective modulator elements to the respective display elements ofblock 18.

In the operation of the system of FIG. 1, the video signal source 12supplies video information to the input stage of the charge transferregister 10. Thhe shift voltage source 14 shifts this video informationfrom stage to stage until the register is fully loaded. Each shiftregister stage connects to the control element ofa modulator. Eachmodulator element, in turn, controls the amount of excitation, providedby the power supply 20, which reaches the display element connected tothat modulator element.

The power supply 20 may be maintained effectively in the off conditionduring the shifting of the charge into the charge transfer register.However, when the register is fully loaded, the power supply 20effectively turns on and supplies power through each modulator elementto the display element connected to that modulator element. The amountof power, as implied above, will depend upon the amount of charge signalstored at the charge transfer stage for the particular display element.

While the circuit of FIG. 1 illustrates only a single charge transferregister and the modulator and display elements associated with thatregister, it is to be appreciated that the invention is equallyapplicable to a larger array of such elements. In such an array. theremay be a plurality of charge transfer registers and separate modulatorelements 16 and display elements 18 associated with each charge transferregister. This plurality of elements 10, 16 and 18 comprises the rows ofthe array.

A two row-by-three element array of the type discussed above is shown inFIG. 2. The charge transfer registers 10a and 10b are illustrated asbucket brigade registers of the general type discussed in U.S. Pat. No.3,683,193, titled Bucket Brigade Scanning of Sensor Array, issued onAug. 8, 1972 to the present inventor.

The vertical scan generator 102 corresponds to the like numbered elementof FIG. 1 of the same patent. The horizontal clock signal source 112also corresponds to the like numbered element in the same patent.

In addition to the above, the present system includes a video signalsource 30 which connects through the conduction paths of N typetransistors such as 30a and 30b to the rows of the array. The modulatorelements may be P type insulated gate field effect transistors such as32a. A gate electrode ofa transistor such as 320 connects to a node 34aof the bucket brigade register. The source electrode of transistor 32a'may connect to the modulator bias supply and the drain electrodethrough a display element 36a and switch 38a to power supply 40.

The various waveforms required for the operation of the systems of FIG.2 are shown in FIG. 6. The video signal provided by source 30 is a timevarying signal.

The operation of the system will be discussed by describing theoperation of the first charge transfer register 10a. Upon theintroduction of vertical synchronization (V-SYNCH') signal into thevertical scan generator and the occurrence of the clock B signal fromthe vertical clock source, a positive voltage V, appears at node 40 ofthe bucket brigade scan generator 102 and a negative signal V remains atnode 42. The signal V remains positive for one line time and then goesnegative. When positive, V turns on N type transistor 44. The bipolarclock pulses from the horizontal clock supply 112 now are transmitted bythe stage 44, 46 and are applied without polarity inversion to alternatetransistors in the register. Electrons from the video signal source 30are drawn into the register through N type transistor 48 during thepositive clock cycle. Transistor 30a serves to control the video signalor serves as an alternate video input gate. When the clock signal goesrelatively negative, electrons are drawn from capacitor 49 viatransistor 50 into capacitor 52. The charges remain in 52 until thepositive clock cycle occurs again causing the negative charges to bedrawn out of 52 and transmitted via transistor 54 to capacitor 56.

The process above continues until the entire register 10a is filled.When this occurs, the vertical clock A and clock Bsignals changepolarity and cause the positive signal at node 40 to transfer to node42. The voltage V becomes negative turning off transistor 44. Thetransistor 46 is connected to a negative bias source 45 and whentransistor 44 goes off, transistor 46 causes node 47 and the clock busconnected thereto to be drawn negative, thereby turning off transistor48 at the input to the register 10a. This isolates the charge transferregister 10a from further input of information. The video signal source30, however, now supplies its information to the second charge transferregister 10b, the horizontal clock signal source 112 causing thisinformation to shift into register 10h.

Returning to charge transfer register 10a, after it is loaded and thetwo input transistors 44 and turned I put of the elements of thedisplay.

off, the switch 38a is closed. This switch may be, for examaple, a Ptype transistor such as shown in FIG. 3. The signal V, applied to thegate electrode of this transistor (this is the signal from node 40 ofthe vertical scan generator) switches to a relatively negative valueafter register a is loaded, effectively closing this switch. However,during the time the register 10a is being loaded, V, is positive,opening switch 38a, effectively disconnecting the power supply 40 fromthe display elements.

When this switch 38a closes, the power supply 40 supplies power throughthe respective display elements such as 36a and through the modulatorelements such as 32a to the return bias supply. The power supply 40 maybe a direct voltage level, which in the case illustrated, would be anegative level. The amount of current that flows through a displayelement will depend upon the voltage at'the gate electrode of itsmodulator element. When this gate electrode is relatively more negative,more current will flow through the display element and when it isrelatively more positive, less current will flow through the displayelement.

The display elements which are illustrated in block form in FIG. 2 maytake any one of a number of different forms. Examples include liquidcrystal elements, electroluminescent elements, light emitting diodes andso on.

An important feature of the present circuit is that the small amount ofsignal available at the respective stages Another feature of the presentsystem is that because the display elements are effectively turned offduring the shifting of new information into the display, there is noblurring of the display due to the input of information. I

In the-example discussed above, it is suggested that the power supply 40may be a direct voltage power supply. However, in some instances, suchas in the case of liquid crystal display elements, it is preferred toemploy alternating voltage excitation to extend the lifetime of theliquid crystal. FIG. 4 illustrates one way this may be done. Itillustrates only a single display location; however, it is to beunderstood that the others are identical.

The modulator, rather than comprising a single transistor such as 320,comprises a dual transmission gate. Such a gate, as is well understoodin the art, comprises a N type transistor 770 and a P type transistor72, the conduction paths of these transistors being connected inparallel. A node such as 340 connects directly to the gate electrodes ofP type transistor 70 and through an inverter 74 to the gate electrode ofN type transistor 72. One end of the parallel connected conduction pathsconnects to a point of reference potential, such as the return biassupply (which in this example may be ground), and the other end ofconduction paths connects to one terminal of a liquid crystal displayelement. The other terminal of the liquid crystal display elementconnects through a switch 76 (corresponding to the switch 38 of FIG. 2),which is common to the entire row, to the alternating current powersupply 78. In the case of a liquid crystal display element, this powersupply may be at a relatively low frequency such as the ordinary 60 Hzpower frequency.

The switch 76 may comprise a dual transmission gate of the same type asalready discussed. For the case of register 10a, the dual transmissiongate connects to node 40 of the vertical scan generator of FIG. 2 andreceives the voltage V,. During the register 10a line time, the voltageV, is relatively positive so that both the P and N type transistors ofthe switch 76 are off. During the remaining line times, V, goesrelatively negative and V, relatively positive, turning on the dualtransmission gate of switch 76. Thus, during these remaining row times,the 60 Hz source 78 supplies power to the liquid crystal through theconduction paths of transistors and 72 in an amount depending upon thecharge present at node 34a.

While a bucket brigade embodiment of the invention is illustrated inFIG. 2, it is of course to be understood that this is representativeonly. Clearly, the same approach is applicable to charge coupled devicesand FIG. 1 is intended to be generic to such devices.

Another form of the invention is illustrated in FIG. 5. Here, thedisplay element, which in the embodiment illustrated comprises a liquidcrystal display element, serves also as one of the charge storageelements of each bucket brigade stage.

The operation of the circuit of FIG. 5 is the same as that ofaconventional bucket brigade circuit. However, after each row is loaded,the respective liquid crystal elements of that row scatter light to anextent proportional to the charge that liquid crystal element isstoring. In this circuit, as in the FIG. 2 circuit, after the completionof a row scan time, the vertical scan generator turns theclock gatetransistor, such as 79, for that row off and the liquid crystal elementscontinue to scatter light for the remaining row times (providing theframe time is sufficiently long so that the liquid crystal elementsretain charge).

A disadvantage of the circuit of FIG. 5 is that during the refreshing ofeach row with new information, the image present in a row becomesblurred due to the moving charge pattern across the liquid crystalelements of that row. The blurred component of the image is only 0.2percent, however, for an array having 500 lines. Another drawback to thesystem of FIG. 5 is that the capacitance of the liquid crystal elementmust be carefully chosen to be compatible with that of the conventionalcapacitors of the bucket brigade register. Also, in the case of liquidcrystal, the direct voltage component across the liquid crystaladversely affects the liquid crystal life. In other forms of solid statedisplay elements, this disadvantage is not present.

While the circuit in FIG. 5 has been illustrated in terms of liquidcrystal elements it is to be understood that other display elementsexhibiting capacitance may be employed instead.

What is claimed is:

1. In combination:

a multiple-stage, charge-transfer analog signal shift register having aninput terminal; means coupled to said terminal for supplying analogsignals thereto;

a plurality of analog signal display elements equal to the number ofstages in said charge transfer register;

a plurality of modulator elements, also equal in number to the number ofcharge transfer stages, each modulator element connected to a differentcharge transfer stage and each controlled by the charge stored in thatcharge transfer stage; and

means for supplying power to each display element through its modulatorelement.

2. In the combintation as set forth in claim 1, said charge-transferregister comprising a bucket brigade register.

3. In the combination as set forth in claim 1, said charge transferregister comprising a charge-coupled device register.

4. In the combination as set forth in claim 1, further including meansfor preventing the application of power to said display elements duringthe shifting of signals into said register.

5. A display system comprising, in combination:

a shift register comprising a row of charge storage elements, at leasttwo per stage;

means for shifting charge signal from storage element to storage elementof said row; and

one storage element of each stage comprising a display element.

6. A display system as set forth in claim 5 wherein said displayelements comprise liquid crystal elements.

7. A display system as set forth in claim 5, further including in saidregister one semiconductor device per storage element, each devicehaving a conduction path connected between two storage elements, and acontrol electrode for controlling the conductance of the conductionpath, each storage element being connected between one end of theconduction path of a semiconductor device and the control electrode ofthat device.

8. In combination:

a multiple-stage analog signal shift register;

a plurality of display elements equal to the number of stages in saidregister, each display element for producing an analog outputproportional to the amplitude of the excitation it receives;

a plurality of modulator elements, also equal in number to the number ofstages in said register, each modulator element connected to a differentregister stage and each controlled by the analog signal stored in thatregister stage; and

means separate from said register for supplying power to each displayelement through its modulator element.

9. In the combination as set forth in claim 8, further including asource of video signals coupled to the input terminal of said shiftregister for supplying to the register the analog signals to be stored.

10. In the combination as set forth in claim 9, each modulator elementcomprising semiconductor means having a transmission path and a controlelectrode, said transmission path connected between a display elementand said means for supplying power and said control element connected toone of said shift register stages.

1]. In the combination as set forth in claim 9, said display elementcomprising liquid crystal display elements.

1. In combination: a multiple-stage, charge-transfer analog signal shiftregister having an input terminal; means coupled to said terminal forsupplying analog signals thereto; a plurality of analog signal displayelements equal to the number of stages in said charge transfer register;a plurality of modulator elements, also equal in number to the number ofcharge transfer stages, each modulator element connected to a differentcharge transfer stage and each controlled by the charge stored in thatcharge transfer stage; and means for supplying power to each displayelement through its modulator element.
 2. In the combintation as setforth in claim 1, said charge-transfer register comprising a bucketbrigade register.
 3. In the combination as set forth in claim 1, saidcharge transfer register comprising a charge-coupled device register. 4.In the combination as set forth in claim 1, further including means forpreventing the application of power to said display elements during theshifting of signals into said register.
 5. A display system comprising,in combination: a shift registeR comprising a row of charge storageelements, at least two per stage; means for shifting charge signal fromstorage element to storage element of said row; and one storage elementof each stage comprising a display element.
 6. A display system as setforth in claim 5 wherein said display elements comprise liquid crystalelements.
 7. A display system as set forth in claim 5, further includingin said register one semiconductor device per storage element, eachdevice having a conduction path connected between two storage elements,and a control electrode for controlling the conductance of theconduction path, each storage element being connected between one end ofthe conduction path of a semiconductor device and the control electrodeof that device.
 8. In combination: a multiple-stage analog signal shiftregister; a plurality of display elements equal to the number of stagesin said register, each display element for producing an analog outputproportional to the amplitude of the excitation it receives; a pluralityof modulator elements, also equal in number to the number of stages insaid register, each modulator element connected to a different registerstage and each controlled by the analog signal stored in that registerstage; and means separate from said register for supplying power to eachdisplay element through its modulator element.
 9. In the combination asset forth in claim 8, further including a source of video signalscoupled to the input terminal of said shift register for supplying tothe register the analog signals to be stored.
 10. In the combination asset forth in claim 9, each modulator element comprising semiconductormeans having a transmission path and a control electrode, saidtransmission path connected between a display element and said means forsupplying power and said control element connected to one of said shiftregister stages.
 11. In the combination as set forth in claim 9, saiddisplay element comprising liquid crystal display elements.